PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362. The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements. Therefore data are shifted down the line when the shift register is activated. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). PATENTED CASE, Free format text: A bidirectional shift register is disclosed which comprises a first and second flip-flop, a first multiplexer having an output coupled to an input of the first flip-flop, and a second multiplexer having an output coupled to an input of the second flip-flop wherein an output of the first flip-flop is coupled to an input of the second multiplexer, an output of the second flip-flop is coupled to an input of the first multiplexer. When the number of bits of the bidirectional shift register becomes large, the additional transistors will occupy a significant amount of chip area, which results in a cost increase. Alternatively, a series of flip-flops can be organized in a last-in-first-out (LIFO) fashion. PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP. In one selection, data stored in the first and second flip-flops swap upon an activation of a clock signal, so that data can be last-in-first-out. In digital circuit, a shift register is a group of flip-flops set up in a linear fashion where an output of a flip-flop is connected to an input of a next flip-flop. Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. Specific embodiments of components and processes are described to help clarify the invention. Shift register is wildly used in integrated circuits. ); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY, Free format text: One application is for programming or reading out electrical fuses, where data intended to be programmed into the electrical fuses are serially clocked in a shift register. The following will provide a detailed description of a bidirectional shift register that can perform either first-in-first-out (FIFO) or last-in-first-out (LIFO) operations without significantly increasing the transistor count therein. shift registers, Digital stores in which the information is moved stepwise, e.g. a first flip-flop and a second flip-flop; a first multiplexer having an output coupled to an input of the first flip-flop; a second multiplexer having a first input coupled to an output of the first flip-flop and an output coupled to an input of the second flip-flop; a third flip-flop having an output coupled to a second input of the second multiplexer, wherein an output of the second flip-flop and an input of the third flip-flop are coupled to each other with no multiplexer disposed therebetween; a fourth flip-flop having an output coupled to an input of the first multiplexer; and. a first data storage unit and a second data storage unit; a first multiplexer having an output coupled to an input of the first data storage unit; a second multiplexer having a first input coupled to an output of the first data storage unit and an output coupled to an input of the second data storage unit; a third data storage unit having an output coupled to a second input of the second muliplexer, wherein an output of the second data storage unit and an input of the third data storage unit are coupled to each other with no multiplexer disposed therebetween; a fourth data storage unit having an output coupled to an input of the first multiplexer; and. This shift register has a few key features: It can be enabled or disabled by driving en pin. shift registers using semiconductor elements, " ", . Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd, Taiwan Semiconductor Manufacturing Co TSMC Ltd. The present invention relates generally to integrated circuit design, and more particularly, to a bidirectional shift register design. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims. MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM. ); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY, Free format text: During the additional clock cycle, first entered data is swapped with later entered data, therefore, during a subsequent normal shifting operation, first entered data will be shifted out last. Data stored in the electrical fuses are first read to the shift register and then serially clocked out. In certain applications, both FIFO and LIFO, i.e. a plurality of multiplexers with outputs coupled to corresponding inputs of the plurality of flip-flops, respectively; a first flip-flop of the plurality of flip-flops having an input coupled to an output of a first multiplexer of the plurality of multiplexers; a second flip-flop of the plurality of flip-flops having an input coupled to an put of a second multiplexer of the plurality of multiplexers, wherein a first input of the second multiplexer is coupled to an output of the first flip-flop; a third flip-flop of the plurality of flip-flops having an input coupled to an output of a third multiplexer of the plurality of multiplexers, wherein the third multiplexer having a first input coupled to an output of the second flip-flop and a second input coupled to an output of the third flip-flop; a fourth flip-flop of the plurality of flip-flops having an input coupled to an output of a fourth multiplexer of the plurality of multiplexers, wherein an output of the fourth flip-flop is coupled to a second input of the second multiplexer and an input of the fourth multiplexer is coupled to the first input of the third multiplexer; a fifth flip-flop of the plurality of flip-flops having an input coupled to an output of a fifth multiplexer of the plurality of multiplexers, wherein an output of the fifth flip-flop is coupled to an input of the first multiplexer and an input of the fifth multiplexer is coupled to the output of the first flip-flop. The above illustration provides many different embodiments or embodiments for implementing different features of the invention. The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. ); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY, PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP. Owner name: In such applications, a conventional circuit is to include both FIFO and LIFO functional circuits with a control signal switching the shift register between the two functions. Although only four and five bits of shift registers are used to illustrate the essence of the present invention, a skilled artisan has no difficulty to expand the idea to other shift registers with more bits. ); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY, PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362, Shift register, electronic device, control method and software program product, Universal spi (serial peripheral interface), Device for maintaining synchronization of plurality of field programmable gate arrays (FPGAs), Operating method of shift register with linear feedback, System and method for achieving circular register shifting based on FIFO, Gray scale generator and driving circuit using the same, Logic integrated circuit for scan path system, Serial input/output semiconductor memory including an output data latch circuit, Digital-to-analog converter with a flexible data interface, Cross feedback latch-type bi-directional shift register in a delay lock loop circuit, Shift register having low power consumption and method of operation thereof, Shift register with selective multiple shifts, Bidirectional shift register, drive circuit using the same, and flat display device, Shift register circuit capable of switching sequence of output signal, Universal Spi (serial Peripheral Interface), Universal SPI (serial peripheral interface), Universal SPI (Serial Peripheral Interface), Limited output address register technique providing selectively variable write latency in DDR2 (double data rate two) integrated circuit memory devices, Programmable logic device logic modules with shift register capabilities, Flip flop circuit and apparatus using a flip flop circuit, High speed fully scaleable, programmable and linear digital delay circuit, Pipe latch circult of multi-bit prefetch-type semiconductor memory device with improved structure, Shift register comprising electrical fuse and related method, Common input/output terminal control circuit, Methods and systems for parallel column twist interleaving, Integrated circuit and method of outputting data from a FIFO, Shift register with reduced area and power consumption, Shift register unit and driving method thereof, scanning driving circuit and display device, RAM functional test facilitation circuit with reduced scale, Register read circuit using the remainders of modulo of a register number by the number of register sub-banks, Counting circuit and address counter using the same, Mode selection circuit, integrated circuit, and electronic device, Programmable logic device including bi-directional shift register, Singnal Selecting Circuit and Semiconductor Memory Device including thereof, Flexible input structure for an embedded memory, Implementation of functions of multiple successive bits of a shift register, Storage device, arithmetic processing unit and control method of storage device, Lapse for failure to pay maintenance fees, Information on status: patent discontinuation, Lapsed due to failure to pay maintenance fee. a third multiplexer having an output coupled to an input of the fourth data storage unit, a first input being coupled to the output of the third data storage unit, and a second input being coupled to the output of the first data storage unit. In fact, adding the additional data swapping clock cycle can be applied to not just LIFO operation mode, it can be used to organize the data pattern in any desired sequence which depends on how the data is swapped. Taiwan Semiconductor Manufacturing Co., Ltd. , TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIW, ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HSIEH, CHEN HUI;CHANG, CHINGWEN;CHENG, WEI CHIA;AND OTHERS;REEL/FRAME:020233/0913, MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM. a third multiplexer having an output coupled to an input of the fourth flip-flop, a first input being coupled to the output of the third flip-flop, and a second input being coupled to the output of the first flip-flop. As such, what is desired is a bidirectional shift register requiring only a small amount of additional circuits over unidirectional shift registers. TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIW, Free format text: Therefore data are shifted down the line when the shift register is activated. Assignors: CHANG, CHINGWEN, CHENG, WEI CHIA, HSIEH, CHEN HUI, LIN, SHIH CHIEH, Digital stores in which the information is moved stepwise, e.g. Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. In summary, the present invention achieves bidirectional shifting by simply adding multiplexers and an additional clock cycle to a conventional shift register. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims. The input data value of the shift register can be controlled by d pin. In digital circuit, a shift register is a group of flip-flops set up in a linear fashion where an output of a flip-flop is connected to an input of a next flip-flop. A control signal determines the multiplexer's input selection. It can shift to the left as well as right when dir is driven. Besides, even though the flip-flop are used in forming the shift registers, a skilled artisan would appreciate other kinds of data storage devices that can latch data upon an activation of a clock signal that may also be used in place of the flip-flop. Shift register is wildly used in integrated circuits. If rstn is pulled low, it will reset the shift register, and output will become 0. However, since the conventional bidirectional shift register requires two sets of flip-flops to perform such bidirectional shifting functions, a transistor count of such conventional bidirectional shift register will be at least doubled. bidirectional, may be required of a shift register. ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HSIEH, CHEN HUI;CHANG, CHINGWEN;CHENG, WEI CHIA;AND OTHERS;REEL/FRAME:020233/0913, Free format text: In view of the foregoing, the present invention provides a bidirectional shift register, which comprises a first and second flip-flop, a first multiplexer having an output coupled to an input of the first flip-flop, and a second multiplexer having an output coupled to an input of the second flip-flop, wherein an output of the first flip-flop is coupled to an input of the second multiplexer, and an output of the second flip-flop is coupled to an input of the first multiplexer. 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